1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a dynamic random access memory (DRAM) having a stacked-capacitor structure in the form of an HSG (hemispherical grained). The invention relates also to a method of manufacturing a DRAM.
2. Description of the Related Art
In the manufacture of DRAMs each having a stacked-capacitor structure, a so-called HSG technology of providing the surface of a storage node in the form of a silicon film with hemispherical grains has recently been developed as one of various methods to increase a memory cell capacitance per unit area by making the surface of a storage node in the form of a stacked capacitor uneven.
In this HGS technology, as disclosed such as in Japanese Patent Laid-Open Publication No. hei7-221034, it is important to remove a natural oxide film off the surface of a silicon film immediately by whatever method before HSG treatment of the silicon film and to form a natural oxide film again after the first natural oxide film has been removed.
Consequently it has been a common practice to carry out, immediately before HSG processing, a surface treatment with dilute fluoric acid to remove the natural oxide film off the silicon film surface and then to terminate the resultant silicon film surface by hydrogen atoms.
A memory cell and a memory-cell fabrication method utilizing this conventional HSG technology will now be described with reference to FIGS. 5(a), 5(b), 6(a)-6(d), 7(a), 7(b), 8(a), 8(b), 9(a) and 9(b) of the accompanying drawings of the present specification. Firstly, FIG. 5(a) shows a layout of the memory cell. In FIG. 5(a), reference number 101 designates an element isolation region; 102, 103, a source-drain region of a MOS transistor; 104, gate electrodes of the MOS transistor formed on a p-type silicon substrate 100 (FIG. 5(b) below) via a gate oxide film; 105, a bit contact; 106, a bit line; 107, storage-node contacts; 108, storage nodes. The entire cell region is covered with a plate electrode (described below in FIG. 8(b)).
Then the memory-cell fabrication method will be described. FIG. 5(b) shows a MOS transistor formed on a p-type silicon substrate 100.
As shown in FIG. 6(a), to secure a good flatness of the substrate surface, an insulation film 110 chiefly of BPSG (boron-phospho-silicate glass) film is formed by CVD and is then treated with heat. When the BPSG film 110 is in direct contact with the substrate 100, phosphorus (P) or boron (Bo) diffuses out after the thermal treatment and, as a result, the sheet resistance of diffusion layer of the already formed source-drain region and the threshold voltage of the already formed transistor deviate off their set values. Consequently it has been customary to take a two-layer structure using a silicon oxide film for the lower layer.
Subsequently, a hole is formed in the bit contact 105 and also a tungsten silicide film as of 2000 angstroms thickness is formed, whereupon the tungsten silicide film is patterned into a desired pattern to form the bit line 106.
Then as shown in FIG. 6(b) a second silicon oxide film 111 as of 2000 angstroms is formed and also a second BPSG film 112 is formed in a 3000 angstroms thickness, and then a thermal treatment as of 900.degree. C. takes place to cause reflow of the second BPSG film 112 in an effort to secure a flatness of the film surface. Further, a third silicon oxide film 113 as of 2000 angstroms is formed.
The third silicon oxide film 113 serves as a mask during a pretreatment (with dilute fluoric acid) process immediately before a subsequent HSG process. Specifically, because the etch rate of the BPSG film with dilute fluoric acid is about ten times that of the silicon oxide film, the most part of the second BPSG film 112 would be etched unless the third silicon oxide film 113 has to a large thickness enough to serve as a mask during the HSG pretreatment, thus lowering the yield markably. The second silicon oxide film 111 serves also to prevent the bit line 106 in the form of the patterned tungsten silicide from displaying due to possible stress simultaneously with reflow of the BPSG film during the thermal treatment of about 900.degree. C. Yet the second silicon oxide film 111 would be essential to improve the reliability (especially corrosion-proofness to salt water) of a packaged device if tungsten silicide is used in the neighboring circuit region as a fuse of a redundancy circuit.
Then as shown in FIG. 6(c), a storage-node contact hole 114 is formed, and a buffered fluoric acid liquid and a Branson cleansing liquid are penetrated into the substrate as a pretreatment process before a phosphorus-doped silicon film is formed. The purpose of these process steps is to ensure an electrical connection between the substrate and the storage node and also to improve the yield partly because of the particle removal effect. At that time, partly because the sidewall surface of the storage-node-forming contact hole 114 is etched a little bit and partly due to the difference of etch rate between the silicon oxide film and the BPSG film, a dent and a lump of hundreds angstroms depth and height are formed. Then a phosphorus-doped silicon film as of 4000 angstroms thickness is formed and is patterned in a desired pattern and, as a result, un-HSG-treated storage nodes 108 are formed.
After that, as shown in FIG. 6(d), for removing a natural oxide film off the surfaces of the storage nodes 108 of phosphorus-doped silicon film and terminating the resultant silicon surface by hydrogen atoms, namely, for HSG treatment, the silicon film surface is treated with dilute fluoric acid and is HSG-treated by silane irradiation and annealing, thus forming on the surfaces of the storage nodes 108 a dent and a lump. Then a capacitance insulation film 115 and a plate electrode 116 of phosphorus-doped silicon film are formed, whereupon these two films are patterned in a desired pattern to obtain a COB-structure (capacitor-over-bitline-structure) memory cell.
However, paying attention to the region except the memory cell, namely, alignment marks to be used in mask alignment and especially to verneir marks which are usually been used up to now, the following problems would be encountered with the conventional memory cell fabrication method using the above-mentioned HSG technology:
A layout of the vernier marks is shown in FIG. 7(a), in which 201 designates patterns to be formed simultaneously with the storage-node-forming masks, and 202, patterns to be formed simultaneously with the storage-node-forming masks.
In the alignment marks like the vernier marks, it has practically been that lower- and upper-layer patterns 201, 202, which should be aligned, overlap each other in part as shown in FIG. 7(a). This is because it is possible to take easy reading of a value of difference between the alignment-marking patterns 201, 202 by reading whether or not two patterns 201, 202 in every individual part overlap with each other.
Various problems with the conventional fabrication method are as follows. FIG. 7(b) is a schematic cross-sectional view showing the shape of the vernier region during the fabrication process corresponding to FIG. 6(b) and immediately after the third silicon oxide film 113 has been formed.
As shown in FIG. 8(a), a hole is formed in the pattern 201 of FIG. 7(a) in the vernier region (i.e., alignment region) simultaneously with the formation of the storage-node-forming contact hole 114. When the substrate 100 is dipped in a buffered fluoric acid liquid and a Branson cleansing liquid as a pretreatment before formation of the phosphorus-doped silicon film, the sidewall surface of the vervier-region pattern 201, like the memory-cell region, is etched a little bit and is thereby provided with a dent and a lump of hundreds angstroms depth and height. Then the phosphorus-doped silicon film 108 for formation of the storage nodes is formed also on the pattern 201.
Then as shown in FIG. 8(b), simultaneously with patterning of the phosphorus-doped silicon film 108 for formation of the storage nodes, the phosphorus-doped film 108 of the vernier region also is patterned using the anisotropic dry etch technique to form the pattern 202 of FIG. 7(a). And in the substrate 100, a recess 301 is formed by overetching the storage nodes; at that time, the phosphorus-doped silicon film 108 of the recess's sidewall surface with a dent and a lump is etched and, as a result, a sidewall 302 of the phosphorus-doped silicon film 108 is formed on the sidewall surface of the recess 301. Further, since the sidewall surface of the recess 301 thus has a dent and a lump, a small sidewall 302a and a large sidewall 302b are formed apart from each other.
FIG. 9(a) shows the structure of FIG. 8(b) having been surface-treated with dilute fluoric acid. As described above, because the etch rate of the BPSG film with dilute fluoric acid is about ten times that of the silicon oxide film, etching of the BPSG films 110, 112 of sidewall surface of the recess 301 of the pattern 201 progresses from the portion uncovered with the sidewall 302. Therefore the small sidewall 302a almost floats in the air as shown in FIG. 9(a), and after the subsequent HSG treatment, this portion is peeled off (FIG. 9(b)) as process garbage, thus lowering the yield.
As long as the BPSG film is not etched during the HSG pretreatment, the sidewall 302 only remains on the sidewall surface of the recess 301 in the pattern 201 without being peeled off. Actually, however, the sidewall 302 was peeled as the HSG pretreatment used dilute fluoric acid. Nevertheless the HSG pretreatment with dilute fluoric acid is indispensable for formation of good HSG-type storage nodes.